Cadence Projects

The Electrical Engineering Department at the University of Tennessee at Chattanooga is a member of the Cadence Design Systems' university program which is designed to facilitate the use of Cadence Design Systems tools by undergraduate and graduate students in engineering courses and in academic research.

Sample Project (Total Ionizing Dose Effects on a K-Band Quadrature LC-Tank VCO):

Radio frequency (RF) systems operating in hostile environments (such as in space) are continuously exposed to ionizing particles that can alter the circuit behavior. Total ionizing dose (TID) irradiation can cause changes in threshold voltage and degradation in ON/OFF state currents of submicron transistors [1-4]. It has been demonstrated that the combined effects of temperature and TID in a commercial 32 nm RF silicon-on-insulator (SOI) technology result in degradation in DC and RF device performance parameters [5]. The single dominant factor affecting the DC and RF performance was determined to be the operating temperature, with the combined effects of elevated temperature and TID showing the most pronounced degradation [5]. Measured TID-induced DC and RF parametric degradation of transistors in the IBM 45 nm CMOS SOI technology have also been used to predict TID-induced degradation in RF circuit performance [4]. Here we extend those results to investigate the measured RF circuit performance versus TID and temperature, further demonstrating the need for combined effects testing in parts characterization and/or qualification.

In order to experimentally verify TID degradation in RF circuits, this work focuses on a K-band
(18-27 GHz) quadrature voltage-controlled oscillator (VCO) designed and fabricated in the IBM 32 nm CMOS SOI process. The Cadence Design Systems tool suite was used to design and layout the VCO. The effects of TID on a K-band quadrature LC-tank VCO are evaluated at three different temperatures. Increases in the TID-induced degradation in frequency, output power and phase noise were observed at elevated temperatures.

A schematic diagram of a complementary LC-tank VCO is shown in Fig. 1. The tank capacitance C_TANK is realized by using tunable (depletion-mode NMOS varactors) and fixed (stacked metal) capacitors. The tank inductance L_TANK is achieved through differential stacked metal inductors to reduce area and maximize the quality factor (Q) [12]. Frequency tuning of the LC-tank is controlled through the bias voltage V_TUNE that adjusts the tunable capacitance. The cross-coupled NMOS (M_N1 & M_N2) and PMOS (M_P1 & M_P2) pairs are used to provide negative resistance to compensate for the parasitic losses in the LC-tank. The NMOS tail current source (M_NTAIL) is used to limit the current flowing through the tank, thereby limiting the power consumed by the VCO.

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