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Cadence University Program

The Electrical Engineering Department at the University of Tennessee is a member of the Cadence Design Systems' university program which is designed to facilitate the use of Cadence Design Systems tools by undergraduate and graduate students in engineering courses and in academic research.

ENEE Courses:

  • ENEE 3770: Advanced Electronics
    • Undergraduate course focused on the design of practical integrated operational amplifier circuits, advanced frequency domain concepts, and negative feedback systems.
    • The culminating design project is to design and simulate, using Cadence Design Systems tools, a CMOS operational amplifier circuit in the ON Semiconductor’s C5F/N 0.5 μm process.
  • ENEE 4999: VLSI Design
    • Undergraduate special topics course focused on very-large-scale integration (VLSI) of circuit technologies. The Cadence Design Systems Virtuoso layout editor is being integrated into the course.
  • ENEE 5910: Advanced Electronics and Integrated Circuits
    • Graduate level course in advanced integrated circuit technologies.

Research Projects:

Faculty and students in the Electrical Engineering Department use Cadence Design Systems tools in their research. Cadence Design Systems tools are used for the design, simulation, and layout of analog, digital, and mixed-signal circuits for microelectronics and embedded systems design and extreme environment design.

Recent Publications (2015-2017) Utilizing Cadence Design Systems Tools :

  • T. D. Loveless, S. Jagannathan, E. X. Zhang, D. Fleetwood, J. Kauppila, L. W. Massengill, “Combined Effects of Total Ionizing Dose and Temperature on a K-band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology,” IEEE Trans. Nucl. Sci., vol. 64, no. 1, pp. 204-211, Jan. 2017.
  • Y P. Chen, T. D. Loveless, A. L. Sternberg, E. X. Zhang, J. S. Kauppila, B. L. Bhuva, W. T. Holman, M. L. Alles, R. A. Reed, R. D. Schrimpf, D. McMorrow, and L. W. Massengill, “Persistent Laser-Induced Leakage in a 20 nm Charge-Pump Phase-Locked Loop (PLL),” IEEE Trans. Nucl. Sci., vol. 64, no. 1, pp. 512-518, Jan. 2017.
  • Y. P. Chen, L. W. Massengill, B. L. Bhuva, W. T. Holman, J. S. Kauppila, and T. D. Loveless, “Single-Event Characterization of 1st and 2nd-order Linear and Bang-bang All-digital Phase-locked Loops (ADPLLs),” proceedings of the 2016 IEEE Radiation Effects on Components & Systems Conference (RADECS), Bremen, Germany, Sept. 2016.
  • S. Jagannathan, N. Mahatme, T. D. Loveless, B. L. Bhuva, and L. W. Massengill, “Hardware Based Empirical Model for Predicting Logic Soft Error Cross-Section,” proceedings of the 2016 IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, Apr. 2016.
  • J. S. Kauppila, T. D. Loveless, T. Haeffner, A. L. Sternberg, D. R. Ball, J. Rowe, T. Assis, H. Jiang, H. Zhang, B. L. Bhuva, M. L. Alles, and L.W. Massengill, “14/16nm FinFET Radiation Response Characterization,” proceedings of the Government Microcircuits Applications and Critical Technology Conference (GOMACTech), Orlando, FL, March, 2016.
  • Y. P. Chen, L. W. Massengill, B. L. Bhuva, W. T. Holman, T. D. Loveless, W. H. Robinson, N. J. Gaspard, and A. F. Witulski, “Single-Event Characterization of Bang-Bang All-Digital Phase-Locked Loops (ADPLLs),” IEEE Trans. Nucl. Sci., vol. 62, no. 6, pp. 2650-2656, Dec. 2015.
  • K. J. Shetler, N. M. Atkinson, W. T. Holman, J. S. Kauppila, T. D. Loveless, A. F. Witulski, B. L. Bhuva, E. X. Zhang, and L. W. Massengill, “Radiation Hardening of Voltage References Using Chopper Stabilization,” IEEE Trans. Nucl. Sci., vol. 62, no. 6, pp. 3064-3071, Dec. 2015.
  • J. S. Kauppila, L. W. Massengill, D. R. Ball, M. L. Alles, R. D. Schrimpf, T. D. Loveless, J. Maharrey, R. C. Quinn, J. D. Rowe, “Geometry-Aware Single-Event Enabled Compact Models for Sub-50 nm Partially Depleted Silicon-on-Insulator Technologies,” IEEE Trans. Nucl. Sci., vol. 62, no. 4, pp. 1589-1598, Aug. 2015.
  • J. Kauppila, J. Maharrey, R. Quinn, T. D. Loveless, T. Haeffner, J. Rowe, D. Ball, M. Alles, and L. Massengill, “Single-Event Measurements and Modeling in 32 nm SOI CMOS,” proceedings of the Government Microcircuits Applications and Critical Technology Conference (GOMACTech), St. Louis, MO, March, 2015.  

 Recent Presentations (2015-2017) Utilizing Cadence Design Systems Tools :

  • INVITED “Hardening-By-Design Techniques for Analog and Mixed-Signal ASICs,” by D. Loveless, presented at the 12th International School on the Effects of Radiation on Embedded Systems for Space Applications (SERESSA), Montreal, Quebec, Canada, Nov. 2016.
  • “A Single-Event Transient Measurement Payload for a 1U CubeSat,” by M. B. Joplin, T. D. Loveless, J. S. Kauppila, and L. W. Massengill, presented at the 2016 Single-Event Effects Symposium, La Jolla, CA, May 2016.
  • INVITED “Radiation Effects and Basic Mitigation Techniques for Mixed-Signal Electronics,” by T. D. Loveless, presented at the 2016 Hardened Electronics and Radiation Technology (HEART) Conference, Monterey, CA, Apr. 2016.
  • INVITED “Hardening-By-Design Techniques for Analog and Mixed-Signal ASICs,” by D. Loveless, presented at the 11th International School on the Effects of Radiation on Embedded Systems for Space Applications (SERESSA), Puebla, Mexico, Dec. 2015.

 

Faculty Contact:
Administrative Contact:
Dr. Daniel Loveless
Karl Fletcher
Phone: (423) 425-2353
Phone: (423) 425-4306
E-mail: daniel-loveless@utc.edu
E-mail: Karl-Fletcher@utc.edu

 

Links:

 

Last Updated: 09/18/2017

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